Title :
A memory efficient array architecture for real-time motion estimation
Author :
Moshnyaga, Vasily G. ; Tamaru, Keikichi
Author_Institution :
Dept. of Electron. & Commun., Kyoto Univ., Japan
Abstract :
A new 2-D array architecture for real-time video picture motion estimation is presented. Due to incorporated concepts of video memory distribution and sharing, the architecture ensures feasible solutions for the HDTV picture format with lower memory requirements. It features minimal I/O pin count, 100% processor utilization and is quite suitable for VLSI implementation
Keywords :
high definition television; motion estimation; parallel architectures; real-time systems; HDTV picture format; VLSI implementation; array architecture; memory requirements; real-time motion estimation; video memory distribution; video picture; video-coding; Bandwidth; Computer architecture; HDTV; Memory architecture; Motion estimation; Parallel processing; Random access memory; Very large scale integration; Video compression; Video sharing;
Conference_Titel :
Parallel Processing Symposium, 1997. Proceedings., 11th International
Conference_Location :
Genva
Print_ISBN :
0-8186-7793-7
DOI :
10.1109/IPPS.1997.580838
