• DocumentCode
    3414094
  • Title

    A memory efficient array architecture for real-time motion estimation

  • Author

    Moshnyaga, Vasily G. ; Tamaru, Keikichi

  • Author_Institution
    Dept. of Electron. & Commun., Kyoto Univ., Japan
  • fYear
    1997
  • fDate
    1-5 Apr 1997
  • Firstpage
    28
  • Lastpage
    32
  • Abstract
    A new 2-D array architecture for real-time video picture motion estimation is presented. Due to incorporated concepts of video memory distribution and sharing, the architecture ensures feasible solutions for the HDTV picture format with lower memory requirements. It features minimal I/O pin count, 100% processor utilization and is quite suitable for VLSI implementation
  • Keywords
    high definition television; motion estimation; parallel architectures; real-time systems; HDTV picture format; VLSI implementation; array architecture; memory requirements; real-time motion estimation; video memory distribution; video picture; video-coding; Bandwidth; Computer architecture; HDTV; Memory architecture; Motion estimation; Parallel processing; Random access memory; Very large scale integration; Video compression; Video sharing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing Symposium, 1997. Proceedings., 11th International
  • Conference_Location
    Genva
  • ISSN
    1063-7133
  • Print_ISBN
    0-8186-7793-7
  • Type

    conf

  • DOI
    10.1109/IPPS.1997.580838
  • Filename
    580838
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3414094