Title :
Accuracy and speed-up of parallel trace-driven architectural simulation
Author :
Nguyen, A.-T. ; Bose, P. ; Ekanadham, K. ; Nanda, A. ; Michael, M.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Trace-driven simulation continues to be one of the main evaluation methods in the design of high performance processor-memory sub-systems. In this paper, we examine the varying speed-up opportunities available by processing a given trace in parallel on an IBM SP-2 machine. We also develop a simple, yet effective method of correcting for cold-start cache miss errors, by the use of overlapped trace chunks. We then report selected experimental results to validate our expectations. We show that it is possible to achieve near-perfect speedup without loss of accuracy. Next, in order to achieve further reduction in simulation cost, we combine uniform sampling methods with parallel trace processing with a slight loss of accuracy for finite-cache timer runs. We then show that by using warm-start sequences from preceding trace chunks, it is possible to reduce the errors back to acceptable bounds
Keywords :
cache storage; digital simulation; parallel architectures; performance evaluation; virtual machines; IBM SP-2; acceptable bounds; architectural simulation; cache miss errors; finite-cache timer; high performance processor-memory; near-perfect speedup; overlapped trace chunks; parallel trace processing; trace-driven simulation; uniform sampling; Analytical models; Compaction; Computational modeling; Costs; Design methodology; Error correction; Parallel processing; Sampling methods; Statistics; Workstations;
Conference_Titel :
Parallel Processing Symposium, 1997. Proceedings., 11th International
Conference_Location :
Genva
Print_ISBN :
0-8186-7793-7
DOI :
10.1109/IPPS.1997.580842