• DocumentCode
    341420
  • Title

    A hybrid DBNS processor for DSP computation

  • Author

    Jullien, G.A. ; Dimitrov, V.S. ; Li, B. ; Miller, W.C. ; Lee, A. ; Ahmadi, M.

  • Author_Institution
    VLSI Res. Group, Windsor Univ., Ont., Canada
  • Volume
    1
  • fYear
    1999
  • fDate
    36342
  • Firstpage
    5
  • Abstract
    This paper introduces a modification to an index calculus representation for the double-base number system (DBNS). The DBNS uses the bases 2 and 3; it is redundant (very sparse) and has a simple two-dimensional representation. An extremely sparse form of the DBNS uses a single non-zero digit to represent any real number with arbitrary precision. In this case the single digit can be identified by its coordinates (indices) in the two-dimensional representation space. The modification proposed in this paper, targeted to DSP inner product computations, uses a single digit representation for the coefficient vector and a 2-digit representation for the data vector. We show that a reduction of over 80% in hardware cost is possible using this hybrid representation compared to the original single-digit technique
  • Keywords
    digital arithmetic; digital signal processing chips; redundancy; table lookup; DSP computation; arbitrary precision; coefficient vector; double-base number system; hardware cost; hybrid DBNS processor; index calculus representation; inner product computations; redundant system; two-dimensional representation space; Arithmetic; Calculus; Cellular neural networks; Costs; Digital signal processing; Finite impulse response filter; Hardware; Neural networks; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
  • Conference_Location
    Orlando, FL
  • Print_ISBN
    0-7803-5471-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1999.777792
  • Filename
    777792