VLSI Architecture for Separable Mellin Transform

Mellin transform (MT) due to its scale invariance property finds itself in a myriad of applications. This work introduces row column decomposition (RCD) based, area efficient MT implementation for real time scale analysis of images. The proposed CORDIC based, multiplierless and fully pipeline architecture sidesteps the transposition operation in conventional RCD method resulting in higher throughput. The critical path in the architecture is an adder and a multiplexer equivalent. The latency depends on the CORDIC depth and image size. The architecture was simulated in Matlab for functional validity and prototyped on FPGA.