Title :
Correcting multiple design errors in digital VLSI circuits
Author :
Veneris, Andreas G. ; Hajj, Ibrahim N.
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Abstract :
With the increase in the complexity of VLSI circuit design, logic design errors can occur during the synthesis process. In this paper we present an efficient test-vector simulation approach for multiple design error diagnosis and correction. We also compare the quality of test vector simulation and BDDs for this problem and show the competitive performance of the former. Experimental results exhibit the robustness of our approach and confirm the theoretical results
Keywords :
VLSI; binary decision diagrams; integrated circuit design; logic CAD; logic simulation; BDDs; digital VLSI circuits; logic design errors; multiple design errors; robustness; synthesis process; test-vector simulation approach; Boolean functions; Circuit simulation; Circuit synthesis; Circuit testing; Computer errors; Computer science; Data structures; Electronic equipment testing; Error correction; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777798
