Title :
A system verification strategy based on the BST infrastructure
Author :
Alves, Gustavo R. ; Ferreira, José M Martins
Author_Institution :
ISEP DEE, Porto, Portugal
Abstract :
A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts
Keywords :
boundary scan testing; field programmable gate arrays; logic simulation; logic testing; timing; BST infrastructure; FPGAs; boundary scan test; functional debug; functional simulation; functioning environments; pin-counts; system verification strategy; timing simulation; Binary search trees; Clocks; Control systems; Field programmable gate arrays; Hardware; Logic testing; Pins; Process control; Prototypes; Timing;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777799
