A statistical critical dimension control at CMOS cell level

Author

Misaka, A. ; Goda, A. ; Matsuoka, K. ; Umimoto, H. ; Odanaka, S.

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

631

Lastpage

634

Abstract

This paper reports a new statistical methodology for controlling the spreads of the CD (critical dimension) distribution in the lithography process. Response surface functions (RSF) for the CD in line and arbitrary gap patterns are introduced. The method allows sensitivity analysis of whole gate patterns at CMOS cell level.

Keywords

CMOS integrated circuits; lithography; semiconductor process modelling; CMOS cell; lithography; response surface function; statistical critical dimension control; CMOS integrated circuits; Circuit simulation; Fabrication; Lithography; Marine vehicles; Pattern analysis; Polynomials; Response surface methodology; Semiconductor device modeling; Statistical analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.554062

Filename

554062

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3414275