Title :
A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs
Author :
Wu, Chung-Yu ; Yu-Yee, Liow
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A novel 1.5-bit (3-level)/cell storage technique is described. This sense amplifier of DRAM can sense the ternary state. Thus, this structure can effectively reduce the bit-cost. The proposed DRAM can be operated at 1.5 V without changing the common DRAM process
Keywords :
CMOS memory circuits; DRAM chips; differential amplifiers; low-power electronics; 1.5 V; bit-cost reduction; dynamic RAM; dynamic ternary sense amplifier; low-voltage CMOS DRAM; multi-level LV CMOS DRAMs; Buildings; CMOS logic circuits; CMOS process; CMOS technology; Costs; Multivalued logic; Operational amplifiers; Random access memory; Read-write memory; Voltage;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777802
