Low power datapath design using transformation similar to temporal localization of SFGs

This paper introduces a methodology that can be employed to reduce power dissipation of datapaths. The method is based on the generation and distribution of registers in circuits with a cyclic signal flow graph where pipelining is not applicable. These additional registers reduce the switching activity and glitch propagation. The method is based on circuit transformations which are usually used to obtain temporally local SFGs. For our application, a digital lattice filter, a reduction of power dissipation by 30% has been achieved. Future work will focus on how to integrate this methodology in our semicustom design flow in an automated way such that a power dissipation based design space exploration is applicable