Title :
A technique for designing self-checking logic for FPGAs
Author :
Lala, P.K. ; Burress, A.L.
Author_Institution :
Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
A technique for designing self-checking combinational logic for implementation in look-up table based FPGAs is presented. The technique is based on mapping Boolean functions into FPGAs such that self-checking features are automatically incorporated into designs, allowing on-line detection of faults in the combinational function block within any CLB of an FPGA, and on the interconnect lines that connect these blocks
Keywords :
Boolean functions; cellular arrays; field programmable gate arrays; logic CAD; table lookup; Boolean functions; CLB; FPGAs; combinational function block; configurable logic block; interconnect lines; look-up table; on-line detection; self-checking logic; Boolean functions; Fault detection; Field programmable gate arrays; Joining processes; Logic design; Multiplexing; Programmable logic arrays; Prototypes; Table lookup; Testing;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777813
