A design for test perspective on memory synthesis

Author

Zarrinch, K. ; Upadhyaya, Shambhu J.

Author_Institution

IBM Corp., Endicott, NY, USA

Volume

1

fYear

1999

fDate

36342

Firstpage

101

Abstract

A novel approach based on a branch and bound technique is presented for transformation of logical memories to mappable physical memories while specified parameters such as area, delay, memory test time and test strategy are satisfied. The proposed algorithm uses the new test parameters to realize a logical memory with a set of physical memories which could be tested within the specified test time using the specified memory test strategy. The proposed framework generates and stores the realized logical memory in structural VHDL

Keywords

application specific integrated circuits; built-in self test; design for testability; hardware description languages; integrated circuit testing; logic testing; tree searching; branch and bound technique; delay; logical memories; mappable physical memories; memory synthesis; memory test time; structural VHDL; test parameters; test perspective; test strategy; Circuit synthesis; Circuit testing; Clustering algorithms; Costs; Delay effects; Digital systems; Libraries; Logic testing; Partitioning algorithms; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.777815

Filename

777815