Title :
Architecture of a hardware module for MPEG-4 shape decoding
Author :
Berekovic, M. ; Jacob, K. ; Pirsch, P.
Author_Institution :
Inst. fur Theor. Nachrichtentech. und Inf., Hannover Univ., Germany
Abstract :
MPEG-4 shape coding comprises context based binary arithmetic encoding (CAE) as its centerpiece. The architecture of a dedicated hardware acceleration module for CAE shape decoding is presented. Synthesis with a 3LM 0.5 μ CMOS library provides a size estimate of 9200 gates plus 3 KB of ROM, which equals approximately 5 mm2 silicon area. The module achieves a throughput rate of 63 MPixel/s
Keywords :
CMOS digital integrated circuits; arithmetic codes; decoding; image coding; multimedia communication; multimedia computing; 0.5 micron; 3 KB; CMOS library; MPEG-4 shape decoding; context based binary arithmetic encoding; dedicated hardware acceleration module; throughput rate; Acceleration; Arithmetic; Computer aided engineering; Decoding; Encoding; Hardware; Libraries; MPEG 4 Standard; Read only memory; Shape;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777827
