DocumentCode
3414481
Title
Incremental Verification Techniques for an Updated Architectural Specification
Author
Mitra, Srobona ; Ghosh, Priyankar ; Dasgupta, Pallab ; Chakrabarti, Partha P.
Author_Institution
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India
fYear
2009
fDate
18-20 Dec. 2009
Firstpage
1
Lastpage
4
Abstract
This paper explores the utility of making use of previously proved component properties and available simulation traces at the component and system level of a composite design for proving a newly added architectural property of the design. We present two techniques of reusing these prior verification results for proving or disproving the architectural property without doing full-scale formal verification of it on the total design from scratch, which runs into capacity issues, or running the already run simulations once again with this new property as an assertion, which is extremely time-consuming and leads to significant wastage of validation effort. We have experimented with our proposed approach on AMBA AHB example and have obtained encouraging results.
Keywords
electronic engineering computing; formal specification; formal verification; logic design; AMBA AHB; architectural specification; formal verification; incremental verification technique; Bismuth; Circuit simulation; Computer science; Data engineering; Databases; Delay; Design engineering; Formal verification; Interconnected systems; Safety;
fLanguage
English
Publisher
ieee
Conference_Titel
India Conference (INDICON), 2009 Annual IEEE
Conference_Location
Gujarat
Print_ISBN
978-1-4244-4858-6
Electronic_ISBN
978-1-4244-4859-3
Type
conf
DOI
10.1109/INDCON.2009.5409403
Filename
5409403
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