Title :
A 4 Gb/s/pin dual-reference simultaneous bidirectional I/O circuit for memory-bus interface
Author :
Woo-Seop Kim ; Jung-Hwan Choi ; Jin-Hyun Kim ; Chang-Hyun Kim ; Soo-In Cho ; Suki Kim
Author_Institution :
Korea Univ., Seoul, South Korea
Abstract :
This paper proposes a receiver with dual reference levels and a pre-emphasis circuit, which reduces ISI and improves input margin and linearity characteristics by 100% for data communication in memory applications. A test chip fabricated with a 0.10 μm 1.8 V CMOS memory process achieves a data rate of 4 Gb/s/pin.
Keywords :
CMOS memory circuits; integrated circuit testing; interference suppression; intersymbol interference; network interfaces; receivers; transceivers; 0.10 micron; 1.8 V; 4 Gbit/s; CMOS memory process; ISI improvement; data communication; data rate; dual reference level receiver; dual-reference simultaneous bidirectional I/O circuit; input margin; linearity characteristics; memory applications; memory-bus interface; pre-emphasis circuit; test chip; Bandwidth; Capacitance; Circuit testing; Crosstalk; Data communication; Driver circuits; Intersymbol interference; Linearity; Pins; Read-write memory;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332769
