A 28.8 Mb/s 4×4 MIMO 3G high-speed downlink packet access receiver with normalized least mean square equalization

Author

Garrett, Deon ; Woodward, Graeme ; Davis, Lisa ; Knagge, G. ; Nicol, Chris

Author_Institution

Bell Labs., Lucent Technol., North Ryde, NSW, Australia

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

420

Abstract

A receiver for high-speed downlink packet access supporting 28.8 Mb/s using QPSK over a 5 MHz frequency selective 4×4 MIMO wireless channel (5.76 b/s/Hz). A key feature is the normalized least mean squares space-time equalizer using a pilot correlator for more accurate adaptation. Fabricated in 0.18 μm 6M CMOS, the core of the chip covers an 11.6 mm² area.

Keywords

3G mobile communication; CMOS integrated circuits; correlators; equalisers; least mean squares methods; packet radio networks; packet reservation multiple access; packet switching; space-time adaptive processing; 0.18 micron; 28.8 Mbit/s; 5 MHz; CMOS chip core area; MIMO 3G high-speed downlink packet access receiver; QPSK; frequency selective MIMO wireless channel; normalized least mean square equalization; normalized least mean squares space-time equalizer; pilot correlator; 3G mobile communication; Correlators; Delay; Downlink; Equalizers; Filters; MIMO; Modulation coding; Multiaccess communication; Transmitting antennas;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332773

Filename

1332773