Title :
CMOS Pass-gate No-race Charge-recycling Logic (CPNCL)
Author :
Seung-Moon Yoo ; Kang, Sung-Mo
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
This paper describes CMOS Pass-gate No-race Charge-recycling Logic (CPNCL). CPNCL realizes low power computation by using a charge sharing method without pre-evaluation problems. CPNCL operates in push-pull mode using CMOS pass-gate logic. 2-input NAND CPNCL shows about 30-50% improvement in power-delay product over other logics. The operation and characteristics of CPNCL are verified by the implementation of a 32 bit adder. CPNCL is more effective than other charge recycling logics in the implementation of a large fan-in random function with arbitrary signal arriving
Keywords :
CMOS logic circuits; VLSI; adders; logic gates; low-power electronics; 2-input NAND function; CMOS pass-gate logic; CPNCL; adder; charge sharing method; large fan-in random function; low energy consumption; low power computation; no-race charge-recycling logic; power-delay product; push-pull mode; Adders; CMOS logic circuits; Energy consumption; Logic circuits; MOS devices; MOSFETs; Power engineering computing; Recycling; Threshold voltage; Timing;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777844
