A 1GHz CMOS analog-front-end for a partial-response read channel

Author

Sun, D. ; Xotta, A. ; Abidi, Abdessalem

Author_Institution

California Univ., Los Angeles, CA, USA

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

430

Abstract

An analog front-end including a continuous-time equalizer to shape the received waveform into a 6-sample target, and a DFE-driven timing recovery loop is presented. With soft Viterbi detection, sensitivity is within 1.5dB of simulations at a rate of 24/25 and user density of 3.4. The 0.35 μm CMOS chip consumes 240mW at 800MHz, and 380mW at 1 GHz clock rates.

Keywords

CMOS analogue integrated circuits; Viterbi detection; channel coding; continuous time filters; decision feedback equalisers; disc drives; hard discs; partial response channels; phase detectors; sample and hold circuits; synchronisation; 1 GHz; 240 mW; 380 mW; 800 MHz; CMOS analog-frontend; DFE-driven timing recovery loop; S/H-based analog delay line; continuous-time equalizer; partial-response read channel; phase detector; received waveform shaping; regenerative comparator; soft Viterbi detection; timing recovery; Decision feedback equalizers; Delay; Detectors; Finite impulse response filter; Frequency; Ground penetrating radar; Phase detection; Phase estimation; Timing; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332778

Filename

1332778