Title :
A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM
Author :
Chang, Ching-Rong ; Wang, Jinn-Shyan
Author_Institution :
Dept. of Electr. Eng., Nat. Chung-Cheng Univ., Taiwan
Abstract :
A new high-speed and low-power dynamic CMOS logic named NHS-PDCMOS logic is proposed. An AOI-type ROM designed in NHS-PDCMOS logic is found to have enhanced speed and power performance than that designed in quasi-domino technique. The power and cycle-time product of the NHS-PDCMOS ROM is only 20.9% that of the quasi-domino ROM
Keywords :
CMOS logic circuits; CMOS memory circuits; VLSI; high-speed integrated circuits; low-power electronics; read-only storage; AOI-type ROM design; NHS-PDCMOS logic; cycle-time product; high-speed dynamic CMOS logic; low-power dynamic CMOS logic; CMOS logic circuits; Circuit noise; Circuit simulation; Logic circuits; Logic design; Logic devices; MOSFETs; Read only memory; Timing; Voltage;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777851
