Title :
Finite state machine partitioning for low power
Author :
Lee, Wai-Kwong ; Tsui, Chi-ying
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong
Abstract :
Clock-gating is an effective approach to reduce power consumption of finite state machines (FSMs) which have plenty of self-loop events. To effectively apply the clock gating technique, the occurrence probability of self-loops in a FSM has to be maximized. In this paper we present a technique based on output partitioning to decompose a FSM into interactive sub-FSMs to increase the self-loop probability of each sub-FSM which in turn reduces the power consumption. Experimental results show that significant increase of the self-loop probability is achieved and power consumption is reduced with a moderate area overhead
Keywords :
clocks; finite state machines; logic CAD; logic partitioning; low-power electronics; sequential circuits; area overhead; clock-gating; finite state machine partitioning; interactive sub-FSMs; low power electronics; occurrence probability; output partitioning; power consumption; self-loop events; Automata; Clocks; Councils; Energy consumption; Energy management; Logic; Power engineering and energy; Sequential circuits; Stationary state; Switching circuits;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777864