Title :
νMOS-based sorters for multiplier implementations
Author :
Rodríguez-Villegas, E. ; Avedillo, M.J. ; Quintana, J.M. ; Huertas, G. ; Rueda, A.
Author_Institution :
Inst. de Microelectron., Centro Nacional de Microelectron., Sevilla, Spain
Abstract :
The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing a (8×8)-multiplier which uses a sorter as the main building block. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits which allows us to improve previous results for multipliers based on a similar architecture
Keywords :
CMOS logic circuits; digital arithmetic; multiplying circuits; sorting; threshold logic; νMOS-based sorters; multiplier implementations; neuron-MOSFET; serial/parallel multiplier; threshold gates; Batteries; Buildings; Built-in self-test; Capacitance; Circuits; Electronic mail; Hardware; Logic design; Sorting; Tin;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777872
