Multiple voltage-based scheduling methodology for low power in the high level synthesis

A methodology for resource-constrained scheduling, in the scenario of function units operating at variable voltages, is presented. Reducing the power consumption while maximizing the hardware sharing is accomplished through a novel formulation. Available parallelism is identified in an initial schedule, and different “zones” with individual weights are created and used for maximally reducing power consumption of the function units whenever a low power schedule is desired for an increased latency. The reduction in throughput due to increased latency is assumed to be compensated through pipelining. There are two main contributions of this work: providing a low complexity algorithm for scheduling with multiple voltages, and providing a mechanism to generate low-power schedules which are realistic, and for which the design of a controller is feasible. The proposed algorithm is applied to standard high-level synthesis benchmarks, and the results indicate significant power savings