A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipeline A/D converter

Author

Nair, Kalyani

Author_Institution

Minnesota Univ., Minneapolis, MN, USA

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

456

Abstract

A 96 dB SFDR 50 MS/s pipeline A/D converter has been designed in a 0.25 μm CMOS process. An improved sample-and-hold and subtractive dither-continuous gain correction (SD-CGC) digital calibration are used to increase linearity. Prototype measurements show that the SNDR increases from 49 dB to 75 dB and the SFDR increases from 62 dB to 96 dB using the technique.

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; integrated circuit design; integrated circuit measurement; pipeline processing; sample and hold circuits; 0.25 micron; CMOS process; SD-CGC; SFDR; SNDR; digitally enhanced CMOS pipeline A/D converter; linearity; prototype measurements; sample-and-hold digital calibration; spurious-free dynamic range; subtractive dither-continuous gain correction digital calibration; Analog-digital conversion; Analytical models; Capacitors; Dynamic range; Error correction; Linearity; Pipelines; Sampling methods; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332791

Filename

1332791

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3414921