Title :
Methodology for analog technology porting including performance tuning
Author :
Francken, K. ; Gielen, G.
Author_Institution :
Dept. of Electr. Eng., Katholieke Univ., Leuven, Belgium
Abstract :
A methodology for technology porting of analog circuit designs is presented. Both the sizing and the layout phase are discussed. The sizing methodology can also be used to tune performances (e.g. minimizing power consumption) when there are margins on the specifications. The methodology is successfully applied to a high-speed ΔΣ A/D converter that is ported from a 0.5 μm to a 0.35 μm CMOS process
Keywords :
CMOS analogue integrated circuits; circuit layout CAD; circuit tuning; high-speed integrated circuits; integrated circuit layout; ΔΣ A/D converter; 0.35 micron; CMOS process; analog circuit designs; analog technology porting; layout phase; performance tuning; power consumption; sizing; specifications; Analog circuits; CMOS process; CMOS technology; Capacitors; Circuit optimization; Circuit topology; Digital circuits; Energy consumption; Equations; Voltage;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777895
