Title :
An 80 MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection
Author :
Dias, V. ; Schwoerer, C.
Abstract :
A 10 b 80 MHz pipeline ADC consumes 22 mA at 1.5 V and occupies a die area of 0.3 mm2 in a 0.13 μm CMOS technology. The ADC is based on a conventional 1.5 b pipeline architecture combined with dynamic-range-doubling and dynamic-reference-selection algorithms.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; integrated circuit measurement; pipeline processing; reference circuits; 0.13 micron; 1.5 V; 1.5 bit; 10 bit; 22 mA; 80 MHz; CMOS technology; dynamic algorithms; dynamic range doubling; dynamic reference selection; pipeline ADC; pipeline architecture; power consumption; CMOS process; CMOS technology; Capacitors; Charge transfer; Clocks; Dynamic range; Energy consumption; Pipelines; Sampling methods; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332794
