Title :
A 14 b-linear capacitor self-trimming pipelined ADC
Author :
Seung-Tak Ryu ; Ray, Sambaran ; Bang-Sup Song ; Gyu-Hyeong Cho ; Bacrania, K.
Author_Institution :
Univ. of California, USA
Abstract :
Capacitor mismatch in a 1.5 b/stage pipelined ADC is self-trimmed with a zero-forcing calibration loop based on ΔΣ polarity detection. Signal-subtracted analog PN error correlation shortens background calibration time by a factor of 10. The 4.2×3.8 mm2 chip in 0.18 μm CMOS exhibits 1 LSB INL at 14 b, 84 dB SFDR at 30 MS/s, and consumes 350 mW at 3 V.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; capacitors; correlation methods; delta-sigma modulation; error analysis; integrated circuit measurement; ΔΣ polarity detection; 0.18 micron; 1.5 bit; 14 bit; 3 V; 3.8 mm; 350 mW; 4.2 mm; CMOS chip; INL; SFDR; background calibration time; capacitor mismatch; chip power consumption; delta-sigma polarity detection; linear capacitor self-trimming pipelined ADC; signal-subtracted analog PN error correlation; zero-forcing calibration loop; Calibration; Capacitance; Capacitors; Clocks; Error correction; Negative feedback; Servomechanisms; Switches; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332795
