Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters

This paper describes a new approach for negating the iteration bound of recursive digital filters. The approach is based on first applying equivalence transforms to the recursive section signal flow graph to determine the maximum allowable pipeline delay for each feedback loop and then selecting bit-parallel arithmetic where pipelined digit-serial computation does not meet these delay limits. Scattered look-ahead pipelining is considered in combination with the proposed method. The resultant structures remain predominantly digit-serial in operation, making the approach ideally suited to designs for programmable logic arrays since high resource efficiency is achieved. Using new digit-serial and bit-parallel multiplier prototypes offering reduced pipeline delay, a 14-bit data path 11-bit coefficient biquadratic filter for the Xilinx XC4010 achieves 36 Msamples.sec^-1 sample processing rate, up to 5 times higher than previously reported results