DocumentCode
341510
Title
An area-efficient versatile Reed-Solomon decoder for ADSL
Author
Huang, Jin-Chuan ; Wu, Chien-Ming ; Shieh, Ming-Der ; Wu, Chien-Hsing
Author_Institution
Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Yunlin, Taiwan
Volume
1
fYear
1999
fDate
36342
Firstpage
517
Abstract
We present an area-efficient, bit-serial VLSI architecture for the t-error-correcting, (n, k)-scalable Reed-Solomon (RS) decoder in GF(2 M) based on the modified Euclidean algorithm. With its ability to support a variety of (n, k) RS codes, this RS decoder is suitable for applications such as the asymmetric digital subscriber line (ADSL) and cable modems
Keywords
Reed-Solomon codes; VLSI; decoding; digital signal processing chips; digital subscriber lines; error correction codes; ADSL; RS codes; Reed-Solomon decoder; area-efficient RS decoder; asymmetric digital subscriber line; bit-serial VLSI architecture; cable modems; error-correcting decoder; modified Euclidean algorithm; Coaxial cables; Code standards; Communication cables; Contracts; Decoding; Equations; Iterative algorithms; Modems; Polynomials; Reed-Solomon codes;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.777942
Filename
777942
Link To Document