40Gb/s amplifier and ESD protection circuit in 0.18μm CMOS technology

Author

Galal, S. ; Razavi, Behzad

Author_Institution

California Univ., Los Angeles, CA, USA

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

480

Abstract

A triple-resonance LC network increases the bandwidth of cascaded differential pairs by a factor of 2√3, yielding a 40 Gb/s CMOS amplifier with a gain of 15 dB and a power dissipation of 190 mW from a 2.2 V supply. An ESD protection circuit employs negative capacitance along with T-coils and pn junctions to operate at 40 Gb/s while tolerating 700 V.

Keywords

CMOS analogue integrated circuits; circuit resonance; electrostatic discharge; millimetre wave amplifiers; wideband amplifiers; 0.18 micron; 15 dB; 190 mW; 2.2 V; 40 Gbit/s; 700 V; CMOS amplifier; ESD protection circuit; T-coils; broadband amplifiers; cascaded differential pair bandwidth; negative capacitance; pn junctions; triple-resonance LC network; Bandwidth; CMOS technology; Capacitance; Circuits; Differential amplifiers; Electrostatic discharge; Gain; Power amplifiers; Power dissipation; Protection;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332803

Filename

1332803

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3415122