An FPGA-based intellectual property protection method at physical design level

Author

Wei, Liang ; Jing, Long ; Weihong, Huang ; Yuanyuan, Liu

Author_Institution

Sch. of Comput. Sci. & Eng., Hunan Univ. of Sci. & Technol., Xiangtan, China

fYear

2012

fDate

24-26 Aug. 2012

Firstpage

400

Lastpage

402

Abstract

An FPGA-based intellectual property protection method at physical design level is presented for ownership identification in IP reuse. The method uses the special physical structure of FPGA for watermark insertion and adds corresponding checkout mechanism in functional circuit for strengthening robustness. Watermark extractor is designed for extracting watermark by analyzing bitstream. The experimental results on Xilinx Virtex II Pro XC2VP4 shows, the presented method has less resource and timing overhead.

Keywords

field programmable gate arrays; industrial property; watermarking; FPGA-based intellectual property protection; IP reuse; Xilinx Virtex II Pro XC2VP4; checkout mechanism; functional circuit; ownership identification; physical design level; resource overhead; strengthening robustness; timing overhead; watermark extractor; watermark insertion; Circuit synthesis; Encryption; Field programmable gate arrays; Robustness; Trademarks; Watermarking; FPGA; IP protection; IP reuse;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Information Processing (CSIP), 2012 International Conference on

Conference_Location

Xi´an, Shaanxi

Print_ISBN

978-1-4673-1410-7

Type

conf

DOI

10.1109/CSIP.2012.6308878

Filename

6308878