Title :
A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process
Author :
Lin, James ; Haroun, Baher ; Jin-sheng Wang ; Mayhugh, T. ; Barr, C.
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
This paper presents a digital PLL with logarithmic time digitizer, digitally-controlled oscillator, and start-up calibration, which achieves a constant damping factor and fractional loop bandwidth over a 0.18 MHz to 600 MHz range of output frequencies and PVT conditions, with output jitter less than 0.04 UIPP. The 0.18 mm2 chip is implemented in 90 nm CMOS, operates over a 0.7 to 2.4 V power supply range and consumes 1.7 mW at 1 V and 520 MHz.
Keywords :
CMOS integrated circuits; UHF oscillators; analogue-digital conversion; calibration; digital phase locked loops; timing jitter; 0.18 to 600 MHz; 0.7 to 2.4 V; 1 V; 1.7 mW; 520 MHz; 90 nm; CMOS; PVT tolerant PLL; clock jitter; constant damping factor; constant fractional loop bandwidth; digitally-controlled oscillator; logarithmic time digitizer; output jitter; self-calibrated digital PLL; start-up calibration; Bandwidth; CMOS process; Clocks; Damping; Delay; Frequency conversion; Jitter; Phase locked loops; Table lookup; Transfer functions;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332807
