Title :
A 0.13μm triple-Vt 9MB third level on-die cache for the Itanium® 2 processor
Author :
Chang, Joana ; Shoemaker, Jonathan ; Haque, Md ; Huang, Meng ; Truong, K. ; Karim, Medles ; Chiu, Shengfen ; Leong, Gloria ; Desai, K. ; Kulkarni, Santosh ; Rao, Akhila ; Rusu, Stefan
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
The 18-way set-associative, single-ported 9 MB cache for the Itanium®2 processor, presented in this paper, uses 210 identical 48 kB sub-arrays with a 2.21 μm2 cell in a 0.13 μm 6M CMOS technology. A staged mode ECC scheme avoids a latency increase in the L3 tag. A high Vt implant improves the read stability and reduces the sub-threshold leakage.
Keywords :
CMOS memory circuits; cache storage; circuit stability; content-addressable storage; error correction codes; microprocessor chips; 0.13 micron; 48 kB; 9 MB; CMOS; Itanium 2 processor; L3 tag latency; high Vt implant; read stability; set-associative cache; single-ported cache; staged mode ECC scheme; sub-threshold leakage reduction; triple-Vt third level on-die cache; Bandwidth; CMOS process; Clocks; Copper; Dielectrics; Error correction; Redundancy; Repeaters; Routing; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332811
