DocumentCode
3415315
Title
A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture
Author
Sungdae Choi ; Kyomin Sohn ; Lee, Min-wuk ; Sunyoung Kim ; Hye-Mi Choi ; Donghyun Kim ; Uk-Rae Cho ; Hyun-Geun Byun ; Hoi-Jun Yoo
Author_Institution
KAIST, Daejeon, South Korea
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
498
Abstract
This paper describes a 2.2 ns search-time, 0.7 fJ/bit/search 0.1 μm CMOS TCAM which uses NOR cells for high-speed coarse search and NAND cells for low-power fine search. A hidden bank selection eliminates the timing penalty for partial activation, a match line repeater enhances the search speed and column decoding enables high memory density.
Keywords
CMOS memory circuits; content-addressable storage; logic gates; low-power electronics; 0.1 micron; 0.7 fJ; 2.2 ns; CMOS CAM; NAND cells; NOR cells; column decoding; fully parallel search; hidden bank selection; high memory density; high-speed coarse search; hybrid TCAM architecture; low-power fine search; match line repeater; partial activation timing penalty; search-time reduction; CADCAM; CMOS process; Clocks; Computer aided manufacturing; Decoding; Energy consumption; Energy efficiency; Prototypes; Repeaters; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332812
Filename
1332812
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