Title :
Architecture and circuit techniques for a reconfigurable memory block
Author :
MAI, Khanh ; Ho, Ron ; Alon, Elad ; Dinesh, P. ; Horowitz, Mark
Author_Institution :
Stanford Univ., CA, USA
Abstract :
A 2 kB reconfigurable SRAM block, using self-timed, pulse-mode circuits capable of emulating a portion of a cache or a streaming FIFO is realized in a 1.8 V 0.18 μm CMOS process and operates at 1.1 GHz (10F04 cycle). The additional logic needed for reconfigurability consumes 26% of the total power and 32% of the total area.
Keywords :
CMOS memory circuits; SRAM chips; cache storage; pulse circuits; reconfigurable architectures; 0.18 micron; 1.1 GHz; 1.8 V; 2 kB; CMOS; cache; pulse-mode circuits; reconfigurability logic; reconfigurable SRAM block; reconfigurable memory block; self-timed circuits; streaming FIFO; Circuits; Decoding; Delay; Field programmable gate arrays; Hardware; Memory architecture; Programmable logic arrays; Random access memory; Reconfigurable logic; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332813
