DocumentCode :
3415332
Title :
Parallel simulated annealing: an adaptive approach
Author :
Knopman, Jonas ; Aude, Julio S.
Author_Institution :
Fed. Univ. of Rio de Janeiro, Brazil
fYear :
1997
fDate :
1-5 Apr 1997
Firstpage :
522
Lastpage :
526
Abstract :
This paper analyses alternatives for the parallelization of the Simulated Annealing algorithm when applied to the placement of modules in a VLSI circuit considering the use of PVM on an Ethernet cluster of workstations. It is shown that different parallelization approaches have to be used for high and low temperature values of the annealing process. The algorithm used for low temperatures is an adaptive version of the speculative algorithm proposed in the literature. Within this adaptive algorithm, the number of processors allocated to the solution of the placement problem and the number of moves evaluated per processor between synchronization points change with the temperature. At high temperatures, an algorithm based on the parallel evaluation of independent chains of moves has been adopted. It is shown that results with the same quality of those produced by the serial version can be obtained when shorter length chains are used in the parallel implementation
Keywords :
VLSI; circuit layout CAD; parallel programming; simulated annealing; VLSI circuit; VLSI design; adaptive algorithm; parallel implementation; parallelization; placement of modules; placement problem; simulated annealing; Adaptive algorithm; Algorithm design and analysis; Analytical models; Circuit simulation; Clustering algorithms; Ethernet networks; Simulated annealing; Temperature; Very large scale integration; Workstations;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Processing Symposium, 1997. Proceedings., 11th International
Conference_Location :
Genva
ISSN :
1063-7133
Print_ISBN :
0-8186-7793-7
Type :
conf
DOI :
10.1109/IPPS.1997.580950
Filename :
580950
Link To Document :
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