DocumentCode
3415346
Title
Per-bit sense amplifier scheme for 1GHz SRAM macro in sub-100nm CMOS technology
Author
Takeda, Kenji ; Hagihara, Y. ; Aimoto, Y. ; Nomura, M. ; Uchida, R. ; Nakazawa, Yoshihiro ; Hirota, Yusuke ; Yoshida, Sigeru ; Saito, Takashi
Author_Institution
NEC Corp., Sagamihara, Japan
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
502
Abstract
A sensing circuit is developed in order to produce a 1 GHz SRAM macro to be used in sub-100 nm CMOS technology nodes. It employs a sense amplifier for each bit-line pair in high-speed operations. The amplifier´s optimized composition consists of just ten transistors and helps to minimize area overhead.
Keywords
CMOS memory circuits; SRAM chips; amplifiers; circuit optimisation; 1 GHz; 90 nm; CMOS; SRAM macro; area overhead minimization; bit-line pair sensing circuit; high-speed operation; per-bit sense amplifier scheme; CMOS process; CMOS technology; Capacitance; Delay effects; Driver circuits; Latches; National electric code; Random access memory; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332814
Filename
1332814
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