Title :
A 90nm dual-port SRAM with 2.04 μm2 8T-thin cell using dynamically-controlled column bias scheme
Author :
Nii, Koji ; Tsukamoto, Yuya ; Yoshizawa, T. ; Makino, Hiroaki
Author_Institution :
Renesas Technology, Itami, Japan
Abstract :
A high-density dual-port SRAM (DP-SRAM) with a 2.04 μm2 cell size is implemented in 90 nm CMOS technology. A dynamically-controlled column-bias scheme is presented, which reduces the active power by 64% and the stand-by current by 93%.
Keywords :
CMOS memory circuits; SRAM chips; low-power electronics; 8T-thin cell; 90 nm; CMOS; DP-SRAM; active power reduction; dual-port SRAM; dynamically-controlled column bias scheme; high-density SRAM; stand-by current reduction; CMOS technology; Capacitance; Current measurement; Decoding; Image processing; Interference; Leakage current; Metallization; Noise reduction; Random access memory;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332817
