A modeling and mapping method for coarse/fine mixed-grained reconfigurable architecture

With the advantage of making reasonable trade-offs between performance and flexibility, reconfigurable architectures have drawn increasing attention. Automatic tools for mapping applications to reconfigurable architectures, however, are rather complicated and challenging work for the reason that mapping tool is always subject to the specific reconfigurable architecture. In this paper, we explore a general modeling and mapping method for coarse/fine mixed-grained reconfigurable architectures (MGRAs) by reinventing the packing method in traditional FPGA software flow and propose a novel modeling method that can describe both fine and coarse reconfigurable architecture in XML format. After a detailed explanation of our proposed modeling and mapping method, we verify our method by implementing a mapping tool for a reconfigurable architecture and manage to map FFT as an application on it. The experiments demonstrate that our proposed method can be applied to MGRA modeling and mapping and is flexible enough to be extended to other reconfigurable architectures.