Title :
A compiler-directed cache coherence scheme using data prefetching
Author :
Lim, Hock-Beng ; Yew, Pen-Chung
Author_Institution :
Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
Abstract :
Cache coherence enforcement and memory latency reduction and hiding are very important problems in the design of large-scale shared-memory multiprocessors. The authors propose a compiler-directed cache coherence scheme which makes use of data prefetching. The cache coherence with data prefetching (CCDP) scheme uses compiler analysis techniques to identify potentially-stale data references, which are references to invalid copies of cached data. The key idea of the CCDP scheme is to enforce cache coherence by prefetching the up-to-date data corresponding to these potentially-stale references from the main memory. Application case studies were conducted to gain a quantitative idea of the performance potential of the CCDP scheme on a real system. They applied the CCDP scheme on four benchmark programs from the SPEC CFP95 and CFP92 suites, and executed them on the Cray T3D. The experimental results show that for the programs studied, the scheme provides significant performance improvements by caching shared data and reducing the remote shared-memory access penalty incurred by the programs
Keywords :
cache storage; parallel processing; performance evaluation; program compilers; shared memory systems; Cray T3D; SPEC CFP92 suite; SPEC CFP95 suite; benchmark programs; cache coherence enforcement; cache coherence with data prefetching scheme; compiler analysis techniques; compiler-directed cache coherence scheme; data prefetching; invalid cached data copies; large-scale shared-memory multiprocessors; main memory; memory latency hiding; memory latency reduction; performance potential; potentially-stale data references; remote shared-memory access penalty reduction; shared data caching; up-to-date data; Algorithm design and analysis; Computer science; Delay; Hardware; Large-scale systems; Optimizing compilers; Prefetching; Program processors; Scheduling algorithm; System performance;
Conference_Titel :
Parallel Processing Symposium, 1997. Proceedings., 11th International
Conference_Location :
Genva
Print_ISBN :
0-8186-7793-7
DOI :
10.1109/IPPS.1997.580970