Very fast pipelined RSA architecture based on Montgomery´s algorithm

Author

Heri, K. Iput ; Bagja, N. Asep ; Purba, Randy S. ; Adiono, Trio

Author_Institution

Electr. Eng. Dept., Bandung Inst. of Technol., Bandung, Indonesia

Volume

02

fYear

2009

fDate

5-7 Aug. 2009

Firstpage

491

Lastpage

495

Abstract

This paper present a design of RSA-encryption using Pipelined radix-2 Montgomery´s architecture. The architecture design exploits the algorithm to achieve high speed and efficient computation. The design separates the computation of Montgomery modular multiplication into different clock cycles to achieve high frequency clock. This design supports input from 1 to 14 block data and efficient in the number of total logic element and register. The design has been successfully verified whether functional Verilog RTL simulation, FPGA timing simulation and run in Signal Tap FPGA simulation. The design occupies logic elements 1157, 1030 registers, and able to run up to 261.85 MHz on Altera Cyclone II EP2C35 F672C6. The proposed design has been successfully synthesized using Synopsys with CMOS 0.18mu technology. The area is 63567.5 mum2 and the delay is 3.35 ns.

Keywords

CMOS digital integrated circuits; cryptography; field programmable gate arrays; Altera Cyclone II EP2C35 F672C6; CMOS technology; FPGA timing simulation; Montgomery algorithm; Signal Tap FPGA simulation; Synopsys; Verilog RTL simulation; logic elements; size 0.18 mum; time 3.35 ns; very fast pipelined RSA encryption; Algorithm design and analysis; CMOS technology; Clocks; Computational modeling; Computer architecture; Field programmable gate arrays; Frequency; Logic design; Registers; Signal design; FPGA; Montgomery; Pipeline Architecture; RSA;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering and Informatics, 2009. ICEEI '09. International Conference on

Conference_Location

Selangor

Print_ISBN

978-1-4244-4913-2

Type

conf

DOI

10.1109/ICEEI.2009.5254686

Filename

5254686