A NoC Architecture for high-speed Dynamic Partial Reconfiguration

Dynamic Partial Reconfiguration (DPR) of FPGA can be used to achieve hardware flexibility and high area utilization. This paper proposes a novel Network on Chip Architecture for DPR (NoC-DPR). The proposed architecture optimizes the NoC network transmission of regular data and configuration bitstreams separately. By transferring the bitstreams parallelly through the NoC and using the DMA method and burst mode to transfer large volume of bitstreams efficiently, our architecture provides a high-speed, location-independent and flexible DPR solution, especially for multi-region DPR design. Results show that the reconfiguration speed of our architecture reaches up to 336.8MB/s and 673.6MB/s respectively when one and two regions reconfiguring parallelly, which outperforms state-of-the-art partial reconfiguration subsystems and can be multiplied in multi-region DPR design. In the end, a prototype system simulating the DPR process of our system has been implemented on Xilinx Virtex5 FPGA platform.