DocumentCode
3416132
Title
Including process-related variability in soft error rate analysis of advanced logic design down to 28 nm based on a foundry PDK
Author
Li, Meng ; Li, Y.F. ; Schrimpf, R.D. ; Fleetwood, D.M.
Author_Institution
Platform Design Autom. Inc., Beijing, China
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
We have developed a statistical soft error rate (SER) analysis that incorporates response surface modeling and a neuron modeling algorithm, which is calibrated to silicon. Experimental results verify faster and more accurate SER estimation.
Keywords
CMOS integrated circuits; calibration; elemental semiconductors; radiation hardening (electronics); response surface methodology; silicon; statistical analysis; SER analysis; Si; advanced logic design; foundry PDK; neuron modeling algorithm; process-related variability; response surface modeling; statistical soft error rate analysis; Analytical models; Computational modeling; Foundries; Integrated circuit modeling; Neurons; SPICE; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6467636
Filename
6467636
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