Title :
Retiming and clock skew for synchronous systems
Author :
Chao, Liang- Fang ; Sha, Edwin Hsing-Mean
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
fDate :
30 May-2 Jun 1994
Abstract :
Retiming and clock skew are both timing optimization methods for synchronous circuitry but are usually applied separately. We use the concept of scheduling to form a common background in the formulation of retiming and clock skew, and to study the interplay between, retiming and clock skew. A methodology to optimise synchronous circuitry with both retiming and clock skew is proposed
Keywords :
logic circuits; logic design; optimisation; scheduling; synchronisation; timing; clock skew; retiming; scheduling; synchronous circuitry; synchronous systems; timing optimization methods; Chaos; Circuit testing; Clocks; Design automation; Flip-flops; Flow graphs; Marine vehicles; Processor scheduling; Propagation delay; Timing;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.408810
