Title :
IEGT design criterion for reducing EMI noise [injection enhancement gate transistor]
Author :
Yamaguchi, Masakazu ; Omura, Ichiro ; Urano, Satoshi ; Umekawa, Shinichi ; Tanaka, Masahiro ; Okuno, Takashi ; Tsunoda, Tetsujiro ; Ogura, Tsuneo
Author_Institution :
Discrete Semicond. Div., Toshiba Corp., Kawasaki, Japan
Abstract :
The EMI noise of an IGBT/IEGT (injection enhancement gate transistor) circuit is significantly reduced by introducing a new device design criterion. The design criterion improves dVCE/dt controllability during the IEGT turn-on transient without sacrificing the featured low saturation voltage of the IEGT structure. The perfectly floating p-well region, as the criterion, prevents the undesirable VGE overshoot and the resultant uncontrollable dVCE/dt. The design criterion has been applied to a 1200 V ultra thin PT-IEGT, and low noise turn-on characteristics have been experimentally obtained. IEGTs with the new criterion enable low noise operation and precise gate control, which are suitable for active gate drive.
Keywords :
electromagnetic interference; insulated gate bipolar transistors; power bipolar transistors; power field effect transistors; semiconductor device noise; transient response; 1200 V; EMI noise reduction; IEGT; IEGT turn-on transient; IGBT/IEGT circuit; active gate drive; gate control precision; injection enhancement gate transistor; low noise operation; low saturation voltage structure; perfectly floating p-well region; ultra thin PT-IEGT; undesirable voltage overshoot; Electromagnetic interference; Insulated gate bipolar transistors; Power FETs; Power bipolar transistors; Semiconductor device noise; Transient response;
Conference_Titel :
Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on
Print_ISBN :
4-88686-060-5
DOI :
10.1109/ISPSD.2004.1332874