DocumentCode
3416678
Title
A novel fully self-aligned process for high cell density trench gate power MOSFETs
Author
Tsui, Bing-Yue ; Gan, Tian-Choy ; Wu, Ming-Da ; Chou, Hui-Hua ; Wu, Zhi-Liang ; Sune, Ching-Tzong
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2004
fDate
24-27 May 2004
Firstpage
205
Lastpage
208
Abstract
A novel self-aligned process for high cell density trench gate power MOSFETs with only four mask layers was proposed. The specific on-resistance can be as low as 0.21 mΩ.cm2 With 1.5 μm cell pitch and 35 V breakdown voltage. Because this process shrinks trench space but not trench width, the quasi-saturation phenomenon is lighter. After optimization of the thickness of n- drift layer and n+ substrate, a specific on-resistance lower than 0.1 mΩ.cm2 with 0.6 μm technology could be expected.
Keywords
power MOSFET; 0.6 micron; 1.5 micron; 35 V; fully self-aligned process; high cell density MOSFET; n+ substrate; n- drift layer thickness; quasi-saturation phenomenon; specific on-resistance; trench gate power MOSFET; trench space reduction; trench width; Power MOSFETs;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on
Print_ISBN
4-88686-060-5
Type
conf
DOI
10.1109/ISPSD.2004.1332901
Filename
1332901
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