Optimization of integrated vertical DMOS transistors for ESD robustness

This paper analyses the ESD robustness of vertically integrated DMOS transistors. The relation between the snapback current (I_sb) and the device layout, and between the thermal failure current (I_tf) and the buried layer process conditions is established. The physical mechanisms responsible for hot spot hopping between two adjacent vertical bipolars; are highlighted. Optimisation for ESD robustness means giving up on R_on. The optimum process and layout conditions are determined.