Field-plate effects on the breakdown voltage of an integrated high-voltage LDMOS transistor

A 700 V double-resurf LDMOS (DR-LDMOS) with double-metal field plates is successfully integrated monolithically in a 1 μ double-level metal (DLM) Bi-CMOS process for use in HV off-line switching applications. The process and device parameters, which determine the best-in-class specific on-resistance of lower than 200 mohm-cm², and a robust breakdown voltage of greater than 700 V, were optimized and addressed in our 1^st generation DR-LDMOS with single-level metal (SLM) process. It is found, during the DLM process development, that breakdown voltage begins to show significant degradation after stress when a 2^nd layer of dielectric layer (ILD-1) is added on top of Metal-1, as opposed to no degradation when there was no ILD-1 on top of Metal-1. This paper presents the re-optimization of DR-LDMOS with new Metal-2 field plate designs with respect to Metal-1 and ILD-1 to maintain a stable and robust breakdown voltage (BV) after stress.