DocumentCode
3416801
Title
A study of STI stress impact on DC performance of nano-scale NMOS
Author
Yun-Juan Yu ; Wen-Jun Li ; Xia Fang
Author_Institution
Key Lab. for RF Circuits & Syst. of Minist. of Educ., Hangzhou Dianzi Univ., Hangzhou, China
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
This work investigates the impact of STIW (the width of shallow-trench-isolation) on DC behavior of nano-scale device. Based on theoretical analysis, several devices with different STIW and fingers based on 65nm CMOS process were designed. The test results prove that it is very important to consider the influence of STIW especially for threshold voltage model of nano-scale device with one finger.
Keywords
CMOS integrated circuits; MOSFET; stress analysis; CMOS process; DC performance behaviour; STI stress impact; STIW; nanoscale NMOS device; shallow-trench-isolation width; size 65 nm; threshold voltage model; CMOS integrated circuits; CMOS process; Fingers; Layout; MOS devices; Semiconductor device modeling; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6467669
Filename
6467669
Link To Document