Title :
Reduced stall MIPS architecture using pre-fetching accelerator
Author :
Zulkifli, M. ; Yudhanto, Y. ; Soetharyo, N.A. ; Adiono, T.
Author_Institution :
Sch. of Electr. Eng. & Inf., Inst. Teknol. Bandung, Bandung, Indonesia
Abstract :
This paper describes the design of a MIPS architecture with a small number of stall. Stall frequently happens in pipeline architecture which results in larger clock cycles. In this paper we significantly reduced stall by introducing pre-fetching unit. This unit reduces stall by concurrently reading three instructions and check their possibility of stall. If stall is detected, this unit then changes the sequence of executed instructions. Furthermore, we also employ forwarding and memory hazard detection units to further reduce stall. In order to increase the processor functionality and performances, especially for RSA security application, we include two new instructions 32-bit mult and mod. The design has been successfully implemented in FPGA DE2 Board (Terasic) and standard call CMOS 0.13u. As system verification, we successfully execute bubble sort program and RSA encryption. The system implementation reach the maximum frequency of 714 MHz.
Keywords :
computer architecture; cryptography; formal verification; multiprocessing systems; pipeline processing; storage management; 32-bit mult; FPGA DE2 Board; RSA encryption; RSA security; Terasic; bubble sort program; forwarding units; memory hazard detection units; mod; pipeline architecture; prefetching accelerator; processor functionality; stall MIPS architecture; standard call CMOS; system verification; Acceleration; Clocks; Cryptography; Field programmable gate arrays; Frequency; Hazards; Informatics; Microprocessors; Pipeline processing; Security; Pre-fetching accelerator; RSA; pipeline; prediction unit;
Conference_Titel :
Electrical Engineering and Informatics, 2009. ICEEI '09. International Conference on
Conference_Location :
Selangor
Print_ISBN :
978-1-4244-4913-2
DOI :
10.1109/ICEEI.2009.5254742