DocumentCode :
3417050
Title :
Reduced pull-in time of phase-locked loops with a novel nonlinear phase-frequency detector
Author :
Liu, Lechang ; Li, Binhong
Author_Institution :
Dept. of Electron. Eng., Shanghai Jiao Tong Univ., China
Volume :
5
fYear :
2005
fDate :
4-7 Dec. 2005
Abstract :
A novel nonlinear phase-frequency detector (PFD) is presented to achieve a fast-switching phase-locked loop (PEE) based frequency synthesizer. Compared with the conventional nonlinear PFD, the proposed topology can further reduce the PEE acquisition time while the loop stability remains unchanged. Moreover, the new topology can decrease the capacitance value and the charge-pump current to 1/k of a conventional one as the loop bandwidth increases k times, thus saving substantial chip area and power consumption.
Keywords :
circuit stability; frequency synthesizers; phase detectors; phase locked loops; capacitance value; charge-pump current; frequency synthesizer; loop bandwidth; loop stability; nonlinear phase-frequency detector; phase-locked loops; pull-in time reduction; Bandwidth; Capacitance; Charge pumps; Energy consumption; Frequency synthesizers; Phase detection; Phase frequency detector; Phase locked loops; Stability; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings
Print_ISBN :
0-7803-9433-X
Type :
conf
DOI :
10.1109/APMC.2005.1607060
Filename :
1607060
Link To Document :
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