DocumentCode
3417131
Title
An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem
Author
Majumder, Turbo ; Sarkar, Souradip ; Pande, Partha ; Kalyanaraman, Ananth
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
fYear
2010
fDate
7-9 July 2010
Firstpage
89
Lastpage
96
Abstract
Traveling Salesman Problem (TSP) is a classical NP-complete problem in graph theory. It aims at finding a least-cost Hamiltonian cycle that traverses all vertices of an input edge-weighted graph. One application of TSP is in breakpoint median-based Maximum Parsimony phylogenetic tree reconstruction, wherein a bounded edge-weight model is used. Exponential algorithms that apply efficient heuristics, such as branch-and-bound, to dynamically prune the search space are used. We adopted this approach in an NoC-based implementation for solving TSP targeted towards phylogenetics taking advantage of the fine-grained parallelism and efficient communication network. The largest fraction of the solution time for TSP is accounted for by a particular lower bound calculation operation that uses the graph´s adjacency matrix. In this paper, we present the design and implementation of the processing elements with a highly optimized lower bound computation kernel and evaluate its performance. Additionally, we explore two major NoC architectures -mesh and quad-tree - and show that the latter is more suitable for this application domain.
Keywords
Acceleration; Communication networks; Design optimization; Graph theory; Kernel; NP-complete problem; Network-on-a-chip; Parallel processing; Phylogeny; Traveling salesman problems;
fLanguage
English
Publisher
ieee
Conference_Titel
Application-specific Systems Architectures and Processors (ASAP), 2010 21st IEEE International Conference on
Conference_Location
Rennes, France
ISSN
2160-0511
Print_ISBN
978-1-4244-6966-6
Electronic_ISBN
2160-0511
Type
conf
DOI
10.1109/ASAP.2010.5540797
Filename
5540797
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